The changes at a glance:
- Shutdown pin (pin 4) of the DC / DC controller U502 (LM2733Y) is now correctly connected to VIN (pin 5) instead of GND. With V3.0 this led to a permanent deactivation of the chip and no bias voltage was supplied to the SiPM. A simple workaround, namely bending up pin 5 and connecting it to the neighboring pin 4, worked perfectly.
- The L501 choke, which was incorrectly placed in V3.0, prevented the effective smoothing of the chopped output voltage of the DC / DC converter. The choke has now correctly moved behind the smoothing capacitor C501.
- A big problem with all board layouts up to and including V3.0 became clear in tests with two detectors: The output of the discriminator of channel 2 (3.3V CMOS, 100ns length) ran as trace in the first inner layer directly underneath the comparator IC U2 and thereby induced a signal in channel 1 whenever channel 2 triggered. The aggressive signal EVT_XOR slipped a little closer to the sensitive comparator input in V3.0, so that the problem was only recognized here. The following remedy was created: The inner layers 1 and 4 (the PCB has a total of 6 layers) were swapped with the inner layers 2 and 3, so that the GND and VCC layers (1 and 4), which are as continuous as possible, act as shielding between the outer layers (top , bot) and the inner signal layers (2,3) act. In addition, the aggressive signals EVT_XOR and EVT_AND have been relocated in such a way that radiation through gaps or holes (e.g. through the free-standing area around vias) is no longer possible. All steep-edged digital signals such as EVT_XOR, EVT_AND and TIME_MEAS_N have been equipped with additional series termination resistors on the transmission side in order to preserve the signal (or better, edge) integrity when routing over longer distances of the PCB.
- Space for 0R resistors (R115 / R215) to bridge the polarity switches has been provided. This is intended to offer a simple assembly variant if no polarity switching is required. In this case, the input must be assigned a signal of fixed polarity, namely negative pulses (U100 / U200 equipped) or positive pulses (U100 / U200 + GG network unequipped).
Further updates will follow shortly when the PCB has been assembled and fully tested.